Mitigating Cache Side-Channel Leakage in Speculative Execution Pipelines via Hardware-Enforced Memory Access Partitioning

Abstract

Speculative execution vulnerabilities, exemplified by Spectre-class and Meltdown-class exploits, continue to undermine the security guarantees of modern out-of-order processors despite numerous microcode patches and compiler-level mitigations. This paper formalizes the threat model for transient execution attacks targeting shared last-level cache (LLC) structures and proposes a hardware-enforced memory access partitioning (HMAP) mechanism that isolates speculative memory traces at the microarchitectural level. HMAP integrates a tagged partition table within the cache hierarchy, enforced by a lightweight finite-state machine embedded in the memory order buffer. Evaluated across SPEC CPU 2017 benchmarks and a suite of synthetic side-channel workloads, HMAP achieves a 94.7% reduction in exploitable cache timing covert channels while incurring a mean runtime overhead of 2.3%, demonstrating practical deployability for security-critical computing environments.